Conventionally, the ECC (Error Checking and Correcting) function has extensively been used in NAND flash memories. The ECC function is disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication Nos. 2003-067260 and 2000-348497.
Also, a memory system in which a plurality of types of memories are integrated into one chip is known. An example is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2006-286179. The system disclosed in this reference includes a NAND flash memory as a main memory, and an SRAM as a data buffer. In addition, the NAND flash memory has the ECC function. Error correction is performed when transferring data from the NAND flash memory in order to read out the data. Also, parity is generated when transferring data from the SRAM to the NAND flash memory in order to write the data.
This arrangement requires at least one data buffer (SRAM cell array), and sometimes includes two data buffers in order to increase the data throughput. However, the circuit area increases because the SRAM must be needed.